1. Field
The embodiment relates to signal processing methods and devices and analog/digital converting devices. More particularly, the embodiment relates to signal processing method and device for processing a time-domain signal, and an analog/digital converting device for converting a time-domain signal to a digital value.
2. Description of the Related Art
Techniques such as Pulse Width Modulation (PWM) have conventionally been known whereby analog signal information is represented along the time axis of a time-domain signal such as a pulse.
Where the time axis of a time-domain signal is used to represent analog signal information, the analog signal can be processed at low voltage, compared with the case where the voltage axis is used to represent analog signal information. This kind of technique has been attracting attention as a result of the recent development of higher-speed hardware enabling improved time resolution.
As such techniques of representing analog signal information along the time axis, a method has been known wherein, for example, the pulse width or pulse interval of a time-domain signal such as a pulse signal is used to represent analog signal information.
FIG. 6 illustrates an exemplary case where the pulse width carries analog signal information.
In the illustrated example, numerical values from “0” to “8” are expressed within a unit time (full-scale time) TF that carries one item of analog signal information. In this case, if the pulse width of an input pulse signal contains, for example, five time resolutions ΔT of a signal processing circuit as shown in the figure, then the input pulse signal represents “5”.
An AD (Analog/Digital) converting device has been known as one of such signal processing circuits that utilize the pulse width of a time-domain signal as indicative of analog signal information.
FIG. 7 is a circuit diagram exemplifying a conventional AD converting device.
The AD converting device 50 includes flip-flop circuits (hereinafter abbreviated as FFs) 51 to 55, buffers 60 to 63, an inverter 70, and an encoder 71.
The FFs 51 to 55 each comprise a D flip-flop, for example, and the buffers 60 to 63 are each constituted by a two-stage inverter.
The FF 51 is input at all times with “1” at its terminal D and is also input with a time-domain signal at its terminal C. When the time-domain signal changes from “0” to “1”, “1” is captured from the terminal D, held by the FF 51, and also output from the output terminal Q. A reset signal is input to the terminal R, and when the reset signal turns to “1”, the output at the terminal Q of the FF 51 is reset to “0”.
The output signal from the output terminal Q of the FF 51 is input to the buffer 60. The state of a node n10 on the input side of the buffer 60 is transmitted to a node n11 after a delay corresponding to the delay time of the buffer 60, transmitted to a node n12 after a delay corresponding to the delay times of the buffers 60 and 61, transmitted to a node n13 after a delay corresponding to the delay times of the buffers 60 to 62, and transmitted to a node n14 after a delay corresponding to the delay times of the buffers 60 to 63. The delay time provided by each of the buffers 60 to 63 determines the time resolution of the AD converting device 50.
The terminals C of the FFs 52 to 55 are input with the inverted time-domain signal through the inverter 70. Also, the terminals D of the FFs 52 to 55 are connected to the nodes n11 to n14, respectively.
Thus, at the time the time-domain signal falls, the states of the nodes n11 to n14 are captured and held by the respective FFs 52 to 55.
The reset signal is also input to the terminals R of the FFs 52 to 55. When the reset signal turns to “1”, the FFs 52 to 55 are all reset to “0”.
Output signals P10 to P13 from the output terminals Q of the respective FFs 52 to 55 are input to the encoder 71. In synchronism with the rise of a clock signal, for example, the encoder 71 captures the output signals P10 to P13 of the FFs 52 to 55.
In FIG. 7, the four buffers 60 to 63 and the FFs 52 to 55 for storing the states of the respective nodes n11 to n14 are illustrated for simplicity of illustration; in practice, the number of the buffers and of the FFs may be increased as desired.
Operation of the AD converting device 50 will be now described.
FIG. 8 is a timing chart exemplifying the operation of the conventional AD converting device.
The figure shows the states of individual signals in the above AD converting device 50, wherein N10 to N14 indicate signals appearing at the respective nodes n10 to n14 shown in FIG. 7. Also, TF indicates the full-scale time, and the pulse width of the time-domain signal within this full-scale time represents analog signal information. TD indicates the time necessary for the signal processing by the encoder 71 and the resetting of the FFs 51 to 55.
When the reset signal is at “1”, the FFs 51 to 55 are all reset, so that the signals N10 to N14 and the output signals P10 to P13 all remain at “0”. The reset signal turns to “0” thereafter, and when the time-domain signal turns to “1”, the signal N10 at the node n10 changes to “1” synchronously with the rise of the time-domain signal (timing T20).
The change of the signal state is propagated to the nodes n11 to n14 while being successively delayed for the delay time of the buffers 60 to 63, and as a consequence, the signals N11 to N14 change to “1” in order. The states of the nodes n11 to n14 are captured by the respective FFs 52 to 55 and are output as the output signals P10 to P13 in synchronism with the fall to “0” of the time-domain signal. By counting at this time the number of output signals whose state is “1”, among the output signals P10 to P13, it is possible to specify, as a discrete value, up to which of the buffers 60 to 63 the state “1” has propagated during the period from the rise to the fall of the time-domain signal. Thus, the pulse width of the time-domain signal is digitized using the delay time of each buffer as a unit. With the circuit exemplified in FIG. 7, numerical values from “0” to “4” can be expressed by means of the output signals P10 to P13.
The time-domain signal turns to “0” at timing T21 within the first full-scale time TF. By this time, the signals N11 to N13 have changed to “1”, but the signal N14 still remains at “0” because of the delay time. In this case, therefore, the three output signals P10 to P12 turn to “1” while the output signal P13 remains at “0”. Accordingly, the pulse width of the time-domain signal represents the digital value “3”.
After a lapse of the full-scale time TF for the first pulse of the time-domain signal (timing T22), the encoder 71 captures the output signals P10 to P13 in synchronism with the rise of the clock signal and renders the captured data in a desired format, for example, in binary code (timing T23). When the reset signal turns to “1” (timing T24) during the time TD, the FFs 51 to 55 are all reset, so that the signal N10 and the output signals P10 to P13 all turn to “0”. The reset signal again turns to “0” thereafter, and when the time-domain signal changes to “1”, signal processing of the next full-scale time TF starts (timing T25). In the second full-scale time TF, the time-domain signal changes to “0” at timing T26. At this time, the signals N11 and N14 are in the state “1” and the signals N12 and N13 are in the state “0”. Accordingly, the output signals P10 and P13 turn to “1” while the output signals P11 and P12 remain at “0”. After a lapse of the full-scale time TF for the second pulse of the time-domain signal (timing T27), the output signals P10 to P13 are captured by the encoder 71 (timing T28). The signal P13 turns to “1” because the signal N14, which changed to “1” during the first full-scale time TF, remains in the same state and the resetting at timing T24 is not propagated yet at timing T26, and not because the rise to “1” of the time-domain signal has been propagated. To enable proper signal processing in such a situation, the encoder 71 may be provided with a mechanism whereby the output signals P10 to P13 are checked in this order to determine whether any signal assumes the state “0” indicating that the resetting has already been propagated at timing T26, and if the state “0” is detected, the values of the succeeding output signals are all corrected to “0”. In the above instance, the output signal P11 is “0”, and accordingly, the encoder 71 corrects the output signals P12 and P13 to “0”, whereby the digital value “1” is derived as the pulse width of the time-domain signal.
In cases where analog signal information is represented along the time axis of a time-domain signal as in the conventional method, the S/N ratio is proportional to the full-scale time and is inversely proportional to the time resolution. If the full-scale time is prolonged, however, the signal processing speed lowers, and thus the full-scale time should not be substantially prolonged. Also, the time resolution has a limit determined by the operating speed and power consumption of devices such as transistors, giving rise to a problem that the time resolution cannot be set finely as desired.
Further, where a time-domain signal generated by a signal generating circuit is processed by a signal processing circuit such as the AD converting device shown in FIG. 7, for example, a problem also arises in that a pulse width difference occurs due to a difference between the threshold used at the signal generating side to discriminate between “1” and “0”, and the threshold used at the signal processing side.
FIG. 9 illustrates such a pulse width difference attributable to a difference between the thresholds.
If the threshold used at the signal generating side to discriminate between “1” and “0” differs from that used at the signal processing side, a difference (offset) occurs between a pulse width tw10 detected at the signal generating side and a pulse width tw11 detected at the signal processing side, as shown in the figure, for example. The offset is a cause of lowering in the signal processing accuracy.
Also, it is occasionally the case that a pulse width offset occurs due to a difference (skew) between the time periods needed to process the rising and falling edges, respectively, of the time-domain signal in the signal processing circuit.
In the conventional AD converting device, for example, the rise of the time-domain signal and the rise of the signal N10 should ideally take place at the same timing, and also the fall of the time-domain signal and the change of the output signals P10 to P13 should ideally take place at the same timing, as shown in the timing chart of FIG. 8. In practice, however, delay exists between the rise of the time-domain signal and the actual output of “1” from the FF 51 and also between the fall of the time-domain signal applied to the FFs 52 to 55 through the inverter 70 and the capture of the states of the nodes n11 to n14 by the respective FFs, and these delays are not exactly equal in length. A problem therefore arises in that the pulse width of the time-domain signal is digitized inclusive of the pulse width difference caused by the delay.